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FEATURES
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LT3029 Dual 500mA/500mA Low Dropout, Low Noise, Micropower Linear Regulator DESCRIPTION
The LT(R)3029 is a dual, micropower, low noise, low dropout linear regulator. The device operates either with a common input supply or independent input supplies for each channel, over an input voltage range of 1.8V to 20V. Each output supplies up to 500mA of output current with a typical dropout voltage of 300mV. Quiescent current is well controlled in dropout. With an external 10nF bypass capacitor, output noise is only 20VRMS over a 10Hz to 100kHz bandwidth. Designed for use in battery-powered systems, the low 55A quiescent current per channel makes it an ideal choice. In shutdown, quiescent current drops to less than 1A. Shutdown control is independent for each channel, allowing for flexible power management. The LT3029 optimizes stability and transient response with low ESR ceramic output capacitors, requiring a minimum of only 3.3F The regulator does not require the addition . of ESR, as is common with other regulators. Internal circuitry provides reverse-battery protection, reverse-current protection, current limiting with foldback and thermal shutdown. The device is available as an adjustable output voltage device with a 1.215V reference voltage. The LT3029 is offered in the thermally enhanced 16-lead MSOP and 16-lead, low profile (4mm x 3mm x 0.75mm) DFN packages.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
Output Current: 500mA per Channel Low Dropout Voltage: 300mV Low Noise: 20VRMS (10Hz to 100kHz) Low Quiescent Current: 55A per Channel Wide Input Voltage Range: 1.8V to 20V (Common or Independent Input Supply) Adjustable Output: 1.215V Reference Voltage Very Low Quiescent Current in Shutdown: <1A per Channel Stable with 3.3F Minimum Output Capacitor Stable with Ceramic, Tantalum or Aluminum Electrolytic Capacitors Reverse-Battery and Reverse Output-to-Input Protection Current Limit with Foldback and Thermal Shutdown Tracking/Sequencing Capability: Compatible with LTC292X Power Supply Tracking ICs Thermally Enhanced 16-Lead MSOP and 16-Lead (4mm x 3mm) DFN Packages
APPLICATIONS
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General Purpose Linear Regulator Battery-Powered Systems Microprocessor Core/Logic Supplies Post Regulator for Switching Supplies Tracking/Sequencing Power Supplies
TYPICAL APPLICATION
2.5VIN to 1.5V/1.8V Application
DROPOUT VOLTAGE (mV) VIN 2.5V 3.3F IN2 SHDN1 SHDN2 OUT2 10nF BYP2 ADJ2 GND 54.9k 1% 237k 1%
3029 TA01
Dropout Voltage vs Load Current
400 VOUT1 1.8V 500mA 350 300 250 200 150 100 50 0 0 50 100 150 200 250 300 350 400 450 500 OUTPUT CURRENT (mA) 3029 TA01b
3029f
TJ = 25C
IN1
OUT1 LT3029 BYP1 ADJ1
10nF
113k 1% 237k 1%
3.3F
3.3F
VOUT2 1.5V 500mA
1
LT3029 ABSOLUTE MAXIMUM RATINGS
(Note 1)
IN1, IN2 Pin Voltage................................................22V OUT1, OUT2 Pin Voltage .........................................22V Input-to-Output Differential Voltage ........................22V ADJ1, ADJ2 Pin Voltage ............................................9V BYP1, BYP2 Pin Voltage ........................................0.6V SHDN1 , SHDN2 Pin Voltage..................................22V Output Short-Circuit Duration .......................... Indefinite
Operating Junction Temperature (Notes 2, 12) LT3029E ............................................. -40C to 125C LT3029I .............................................. -40C to 125C LT3029H ............................................ -40C to 150C LT3029MP.......................................... -55C to 125C Storage Temperature Range................... -65C to 150C Lead Temperature (Soldering, 10 sec) (MSOP Only)..................................................... 300C
PIN CONFIGURATION
TOP VIEW BYP1 NC OUT1 OUT1 GND OUT2 OUT2 BYP2 1 2 3 4 5 6 7 8 17 GND 16 ADJ1 15 SHDN1 14 IN1 13 IN1 12 IN2 11 IN2 10 SHDN2 9 ADJ2 TOP VIEW BYP1 NC OUT1 OUT1 GND OUT2 OUT2 BYP2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ADJ1 SHDN1 IN1 IN1 IN2 IN2 SHDN2 ADJ2
17 GND
MSE PACKAGE 16-LEAD PLASTIC MSOP
DE PACKAGE 16-LEAD (4mm 3mm) PLASTIC DFN
TJMAX = 125C, JA = 38C/W, JC = 4.3C/W EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB GND
TJMAX = 125C (LT3029E/LT3029I, LT3029MP), JA = 37C/W, JC: 5C/W TO 10C/W TJMAX = 150C (LT3029H), JA = 37C/W, JC: 5C/W TO 10C/W EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB GND
ORDER INFORMATION
LEAD FREE FINISH LT3029EDE#PBF LT3029IDE#PBF LT3029EMSE#PBF LT3029IMSE#PBF LT3029HMSE#PBF LT3029MPMSE#PBF LEAD BASED FINISH LT3029EDE LT3029IDE LT3029EMSE LT3029IMSE LT3029HMSE LT3029MPMSE TAPE AND REEL LT3029EDE#TRPBF LT3029IDE#TRPBF LT3029EMSE#TRPBF LT3029IMSE#TRPBF LT3029HMSE#TRPBF LT3029MPMSE#TRPBF TAPE AND REEL LT3029EDE#TR LT3029IDE#TR LT3029EMSE#TR LT3029IMSE#TR LT3029HMSE#TR LT3029MPMSE#TR PART MARKING* 3029 3029 3029 3029 3029 3029 PART MARKING* 3029 3029 3029 3029 3029 3029 PACKAGE DESCRIPTION 16-Lead (4mm x 3mm) Plastic DFN 16-Lead (4mm x 3mm) Plastic DFN 16-Lead Plastic MSOP 16-Lead Plastic MSOP 16-Lead Plastic MSOP 16-Lead Plastic MSOP PACKAGE DESCRIPTION 16-Lead (4mm x 3mm) Plastic DFN 16-Lead (4mm x 3mm) Plastic DFN 16-Lead Plastic MSOP 16-Lead Plastic MSOP 16-Lead Plastic MSOP 16-Lead Plastic MSOP TEMPERATURE RANGE -40C to 125C -40C to 125C -40C to 125C -40C to 125C -40C to 150C -55C to 125C TEMPERATURE RANGE -40C to 125C -40C to 125C -40C to 125C -40C to 125C -40C to 150C -55C to 125C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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LT3029 ELECTRICAL CHARACTERISTICS
PARAMETER Minimum Input Voltage (Notes 3, 11) ADJ1, ADJ2 Pin Voltage (Notes 3, 4, 9)
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 2)
CONDITIONS ILOAD = 500mA VIN = 2V, ILOAD = 1mA 2.3V < VIN < 20V, 1mA < ILOAD < 500mA (E, I, MP) 2.3V < VIN < 20V, 1mA < ILOAD < 500mA (H) VIN = 2V to 20V, ILOAD = 1mA VIN = 2.3V, ILOAD = 1mA to 500mA VIN = 2.3V, ILOAD = 1mA to 500mA (E, I, MP) VIN = 2.3V, ILOAD = 1mA to 500mA (H) ILOAD = 10mA ILOAD = 10mA ILOAD = 50mA ILOAD = 50mA ILOAD = 100mA ILOAD = 100mA ILOAD = 500mA ILOAD = 500mA
l l l l l l
MIN 1.203 1.191 1.173
TYP 1.8 1.215 1.215 1.215 0.5 2.5
MAX 2.3 1.227 1.239 1.239 5 6 15 32 0.18 0.25 0.22 0.31 0.25 0.34 0.36 0.46 150 250 2 3.5 8 16
UNITS V V V V mV mV mV mV V V V V V V V V A A mA mA mA mA VRMS
Line Regulation (Note 3) Load Regulation (Note 3)
Dropout Voltage VIN = VOUT(NOMINAL) (Notes 5, 6, 11)
0.11
l
0.16
l
0.2
l
0.3
l l l l l l l
GND Pin Current (per Channel) VIN = VOUT(NOMINAL) (Notes 5, 7)
ILOAD = 0mA ILOAD = 1mA ILOAD = 50mA ILOAD = 100mA ILOAD = 250mA ILOAD = 500mA COUT = 10F CBYP = 10nF ILOAD = 500mA, , , BW = 10Hz to 100kHz ADJ1, ADJ2 (Notes 3, 8) VOUT = Off to On VOUT = On to Off VSHDN1, VSHDN2 = 0V VSHDN1, VSHDN2 = 20V VIN = 6V, VSHDN1 = 0V, VSHDN2 = 0V VIN = 2.715V (Avg), VRIPPLE = 0.5VP-P, fRIPPLE = 120Hz, ILOAD = 500mA VIN = 7V, VOUT = 0V VIN = 2.3V, VOUT = -0.1V VIN = -20V, VOUT = 0V VOUT = 1.215V, VIN = 0V
55 90 1.1 2 4.3 10 20 30
Output Voltage Noise ADJ1/ADJ2 Pin Bias Current Shutdown Threshold SHDN1/SHDN2 Pin Current (Note 10) Quiescent Current in Shutdown (per Channel) Ripple Rejection Current Limit (Note 9) Input Reverse Leakage Current Reverse Output Current
100 1.1 0.5 3 0.1
nA V V A A A dB A mA
l l l l
0.20
0.45 0.40 0 0.6 0.01
55
67 1.5
l l
520 1 0.5 10
mA A
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT3029 is tested and specified under pulse load conditions such that TJ TA. The LT3029E is 100% tested at TA = 25C. Performance of the LT3029E over the full -40C to 125C operating junction temperature range is assured by design, characterization and correlation with statistical process controls. The LT3029I is guaranteed over the full -40C to 125C operating junction temperature range. The LT3029MP is 100% tested and guaranteed over the -55C to 125C operating junction temperature range. The LT3029H is tested at 150C operating junction temperature. High junction temperatures degrade operating lifetimes. Operating lifetime is derated at junction temperatures greater than 125C.
Note 3: The LT3029 is tested and specified for these conditions with the ADJ1/ADJ2 pin connected to the corresponding OUT1/OUT2 pin. Note 4: Maximum junction temperature limits operating conditions. The regulated output voltage specification does not apply for all possible combinations of input voltage and output current. When operating at maximum input voltage, limit the output current range. When operating at maximum output current, limit the input voltage range. Note 5: To satisfy minimum input voltage requirements, the LT3029 is tested and specified for these conditions with an external resistor divider (two 243k resistors) for an output voltage of 2.437V. The external resistor divider adds 5A of DC load on the output. Note 6: Dropout voltage is the minimum input to output voltage differential needed to maintain regulation at a specified output current. In dropout, the output voltage equals: VIN - VDROPOUT.
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LT3029 ELECTRICAL CHARACTERISTICS
Note 7: GND pin current is tested with VIN = 2.437V and a current source load. This means the device is tested while operating in its dropout region or at the minimum input voltage specification. This is the worst-case GND pin current. The GND pin current decreases slightly at higher input voltages. Total GND pin current equals the sum of output 1 and output 2 GND pin currents. Note 8: ADJ1/ADJ2 pin bias current flows into the pin. Note 9: The LT3029 contains current limit foldback circuitry. See the Typical Performance Characteristics for current limit as a function of the VIN - VOUT differential voltage. Note 10: SHDN1/ SHDN2 pin current flows into the pin. Note 11: The LT3029 minimum input voltage specification limits dropout voltage under some output voltage/load conditions. See the curve of Minimum Input Voltage in the Typical Performance Characteristics. Note 12: The LT3029 includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature exceeds the maximum operating junction temperature when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability.
TYPICAL PERFORMANCE CHARACTERISTICS
Typical Dropout Voltage
500 GUARANTEED DROPOUT VOLTAGE (mV) 450 DROPOUT VOLTAGE (mV) 400 350 300 250 200 150 100 50 0 0 50 100 150 200 250 300 350 400 450 500 OUTPUT CURRENT (mA)
3029 G01
TJ = 25C, unless otherwise noted.
Guaranteed Dropout Voltage
500 TJ = 150C TJ = 125C 450 400 350 300 250 200 150 100 50 0 0 50 100 150 200 250 300 350 400 450 500 OUTPUT CURRENT (mA)
3029 G02
= TEST POINTS TJ = 150C TJ = 25C
TJ = 25C TJ = -55C
Dropout Voltage vs Temperature
500 450 DROPOUT VOLTAGE (mV) 400 350 300 250 200 150 100 50 IL = 1mA IL = 50mA IL = 10mA IL = 250mA IL = 100mA IL = 500mA QUIESCENT CURRENT (A) 150 125 100 75 50 25
Quiescent Current (per Channel)
VIN = 6V RL = 243k, IL = 5A
VSHDN = VIN
0 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
3029 G03
0 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
3029 G04
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LT3029 TYPICAL PERFORMANCE CHARACTERISTICS
ADJ1 or ADJ2 Pin Voltage
1.239 1.233 QUIESCENT CURRENT (A) ADJ PIN VOLTAGE (V) 1.227 1.221 1.215 1.209 1.203 1.197 1.191 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
3029 G05
TJ = 25C, unless otherwise noted.
Quiescent Current (per Channel)
160 140 120 100 80 60 40 20 0 0 2 4 VSHDN = 0V 6 8 10 12 14 16 18 20 INPUT VOLTAGE (V)
3029 G06
IL = 1mA
TJ = 25C RL = 243k VOUT = 1.215V
VSHDN = VIN
GND Pin Current (per Channel)
1.6 TJ = 25C 1.4 FOR VOUT = 1.215V GND PIN CURRENT (mA) RL = 24.3, IL = 50mA GND PIN CURRENT (mA) 1.2 1.0 0.8 0.6 0.4 0.2 0 0 1 2 34567 INPUT VOLTAGE (V) 8 9 10 RL = 121.5, IL = 10mA RL = 1.215k, IL = 1mA 16
GND Pin Current (per Channel)
TJ = 25C 14 FOR VOUT = 1.215V 12 10 8 6 4 2 0 0 1 2 34567 INPUT VOLTAGE (V) 8 9 10
3029 G08
RL = 2.43, IL = 500mA
RL = 4.05, IL = 300mA RL = 12.15, IL = 100mA
3029 G07
GND Pin Current vs ILOAD
16 14 GND PIN CURRENT (mA) 12 10 8 6 4 2 0 0 50 100 150 200 250 300 350 400 450 500 OUTPUT CURRENT (mA)
3029 G09
SHDN1 or SHDN2 Pin Threshold (On-to-Off)
1.0 0.9 SHDN PIN THRESHOLD (V) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
3029 G10
TJ = 25C VIN = VOUT(NOMINAL) + 1V
IL = 1mA
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LT3029 TYPICAL PERFORMANCE CHARACTERISTICS
SHDN1 or SHDN2 Pin Threshold (Off-to-On)
1.0 0.9 SHDN PIN INPUT CURRENT (A) SHDN PIN THRESHOLD (V) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
3029 G11
TJ = 25C, unless otherwise noted.
SHDN1 or SHDN2 Pin Input Current
1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 SHDN PIN VOLTAGE (V)
3029 G12
TJ = 25C
IL = 500mA IL = 1mA
SHDN1 or SHDN2 Pin Input Current
1.0 0.9 SHDN PIN INPUT CURRENT (A) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
3029 G13
ADJ1 or ADJ2 Pin Bias Current
150 135 ADJ PIN BIAS CURRENT (nA) 120 105 90 75 60 45 30 15 0 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
3029 G14
VSHDN = 20V
Current Limit
2.0 1.8 1.6 CURRENT LIMIT (A) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 INPUT VOLTAGE (V)
3029 G15
Current Limit
2.0 VIN = 7V 1.8 VOUT = 0V 1.6 CURRENT LIMIT (A) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -75 -50 -25 0 25 50 75 100 125 150 175
3029 G16
VOUT = 0V TJ = 25C
TJ = -55C TJ = 125C TJ = 150C
TEMPERATURE (C)
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LT3029 TYPICAL PERFORMANCE CHARACTERISTICS
Reverse Current
300 270 REVERSE CURRENT (A) 240 210 180 150 120 90 60 30 0 -75 -50 -25 0 IOUT 25 50 75 100 125 150 175 IADJ RIPPLE REJECTION (dB) 100 VIN = 0V VADJ = VOUT = 1.215V
TJ = 25C, unless otherwise noted.
Input Ripple Rejection
TJ = 25C 90 IL = 500mA +1V + 50mVRMS RIPPLE V =V 80 CIN = OUT(NOMINAL) BYP 0 COUT = 10F 70 60 50 40 30 20 10 0 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M
3029 G18 3029 G17
COUT = 3.3F
TEMPERATURE (C) IADJ FLOWS INTO ADJ PIN TO GND PIN IOUT FLOWS INTO OUT PIN TO IN PIN
Input Ripple Rejection
100 90 80 RIPPLE REJECTION (dB) 70 60 50 40 30 20 10 0 TJ = 25C IL = 500mA VIN = VOUT(NOMINAL) +1V + 50mVRMS RIPPLE COUT = 10F 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M
3029 G19
Input Ripple Rejection
100 90 VIN = VOUT(NOMINAL) + 1.5V + 0.5VP-P RIPPLE f = 120Hz IL = 500mA
CBYP = 0.01F RIPPLE REJECTION (dB)
80 70 60 50 40 30 20 10
CBYP = 1000pF CBYP = 100pF
0 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
3029 G20
Minimum Input Voltage
2.50 2.25 MINIMUM INPUT VOLTAGE (V) 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
3029 G21
Channel-to-Channel Isolation
100 CHANNEL-TO-CHANNEL ISOLATION (dB) 90 80 70 60 50 40 30 20 10 0 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M TJ = 25C
VOUT = 1.215V IL = 500mA
IL = 1mA
GIVEN CHANNEL IS TESTED WITH 50mVRMS SIGNAL ON OPPOSING CHANNEL, BOTH CHANNELS DELIVERING FULL CURRENT
3029 G22
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LT3029 TYPICAL PERFORMANCE CHARACTERISTICS
Channel-to-Channel Isolation
0 -2 LOAD REGULATION (mV) VOUT1 50mV/DIV -4 -6 -8 -10 -12 -14 -16 -18 IL = 1mA TO 500mA -20 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C)
3029 G24
TJ = 25C, unless otherwise noted.
Load Regulation
VOUT2 50mV/DIV
50s/DIV COUT1 = 10F IL1 = 50mA TO 500mA COUT2 = 10F IL2 = 50mA TO 500mA CBYP1 = CBYP2 = 0.01F VIN = 6V, VOUT1 = VOUT2 = 5V
3029 G23
Output Noise Spectral Density
OUTPUT NOISE SPECTRAL DENSITY (V/ Hz) TJ = 25C COUT = 10F CBYP = 0 IL = 500mA OUTPUT NOISE SPECTRAL DENSITY (V/ Hz) 10 10
Output Noise Spectral Density
TJ = 25C COUT = 10F IL = 500mA VOUT = 5V 1 CBYP = 1000pF
VOUT = 5V
1 VOUT = VADJ
VOUT =VADJ 0.1 CBYP = 0.01F
CBYP = 100pF
0.1
0.01 0.01
0.1
1 10 FREQUENCY (kHz)
100
3029 G25
0.01 0.01
0.1
1 10 FREQUENCY (kHz)
100
3029 G26
RMS Output Noise vs Bypass Capacitor
160 140 OUTPUT NOISE (VRMS) 120 VOUT = 5V 100 80 60 40 20 0 10 100 CBYP (pF)
3029 G27
RMS Output Noise vs Load Current
160 TJ = 25C 140 COUT = 10F CBYP = 0 CBYP = 10nF 120 100 80 60 40 20 1000 10000 0 0.01 0.1 VOUT = 5V VOUT =VADJ 1 10 100 LOAD CURRENT (mA)
3029 G28
VOUT = 1.215V
OUTPUT NOISE (VRMS)
TJ = 25C COUT = 10F IL = 500mA fBW = 10Hz TO 100kHz
VOUT = 5V
VOUT =VADJ
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LT3029 TYPICAL PERFORMANCE CHARACTERISTICS
10Hz to 100kHz Output Noise, CBYP = 0pF TJ = 25C, unless otherwise noted.
10Hz to 100kHz Output Noise, CBYP = 100pF
VOUT 100V/DIV
VOUT 100V/DIV
COUT = 10F IL = 500mA VOUT = 5V
1ms/DIV
3029 G29
COUT = 10F IL = 500mA VOUT = 5V
1ms/DIV
3029 G30
10Hz to 100kHz Output Noise, CBYP = 1000pF
10Hz to 100kHz Output Noise, CBYP = 0.01F
VOUT 100V/DIV
VOUT 100V/DIV
COUT = 10F IL = 500mA VOUT = 5V
1ms/DIV
3029 G31
COUT = 10F IL = 500mA VOUT = 5V
1ms/DIV
3029 G32
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LT3029 TYPICAL PERFORMANCE CHARACTERISTICS
Transient Response, CBYP = 0pF
VOUT DEVIATION 200mV/DIV 50mV/DIV
TJ = 25C, unless otherwise noted.
Transient Response, CBYP = 0.01F
VOUT DEVIATION
LOAD CURRENT DEVIATION 250mA/DIV 250mA/DIV
LOAD CURRENT DEVIATION
VIN = 6V CIN = 10F COUT = 10F
200s/DIV IL = 100mA TJ = 25C VOUT = 5V
3029 G33
VIN = 6V CIN = 10F COUT = 10F
20s/DIV IL = 100mA TJ = 25C VOUT = 5V
3029 G34
Start-Up Time from Shutdown, CBYP = 0pF
Start-Up Time from Shutdown, CBYP = 0.01F
VOUT 1V/DIV
VOUT 1V/DIV
SHDN VOLTAGE 2V/DIV 1ms/DIV IL = 500mA VOUT = 1.5V
3029 G35
SHDN VOLTAGE 2V/DIV 1ms/DIV IL = 500mA VOUT = 1.5V
3029 G36
VIN = 2.5V COUT = 10F RL = 3
VIN = 2.5V COUT = 10F RL = 3
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LT3029 PIN FUNCTIONS
BYP1/BYP2 (Pin 1/Pin 8): Bypass. Use the BYP1/BYP2 pins to bypass the reference of the LT3029 regulator and achieve low output noise performance. Internal circuitry clamps the BYP1/BYP2 pins to 0.6V (one VBE) from ground. A small capacitor from the corresponding output to this pin bypasses the reference to lower the output voltage noise. Using a maximum value of 10nF reduces the output voltage noise to a typical 20VRMS over a 10Hz to 100kHz bandwidth. If not used, this pin must be left unconnected. NC (Pin 2): No Connect. This pin is not connected to any internal circuitry. It may be floated, tied to VIN or tied to GND. OUT1/OUT2 (Pins 3, 4/Pins 6, 7): Output. The outputs supply power to the loads. A minimum 3.3F output capacitor prevents oscillations on each output. Applications with large output load transients require larger values of output capacitance to limit peak voltage transients. See the Applications Information section for more on output capacitance and reverse output characteristics. GND (Pin 5, 17): Ground. The exposed pad (Pin 17) of the DFN and MSOP packages is an electrical connection to GND. To ensure proper electrical and thermal performance, solder Pin 17 to the PCB ground and tie directly to Pin 5. Connect the bottom of the output voltage setting resistor divider directly to GND (Pin 5) for optimum load regulation performance. IN1/IN2 (Pins 13, 14/Pins 11, 12): Inputs. The IN1/IN2 pins supply power to each channel. The LT3029 requires a bypass capacitor at the IN1/IN2 pins if located more than six inches away from the main input filter capacitor. Include a bypass capacitor in battery-powered circuits, as a battery's output impedance rises with frequency. A bypass capacitor in the range of 1F to 10F suffices. The LT3029's design withstands reverse voltages on the IN pins with respect to ground and the OUT pins. In the case of a reversed input, which occurs if a battery is plugged in backwards, the LT3029 acts as if a diode is in series with its input. No reverse current flows into the LT3029 and no reverse voltage appears at the load. The device protects itself and the load. SHDN1 / SHDN2 (Pin 15/Pin 10): Shutdown. Pulling the SHDN1 or SHDN2 pin low puts its corresponding LT3029 channel into a low power state and turns its output off. The SHDN1 and SHDN2 pins are completely independent of each other, and each SHDN pin only affects operation on its corresponding channel. Drive the SHDN1 and SHDN2 pins with either logic or an open collector/drain with pull-up resistors. The resistors supply the pull-up current to the open collectors/drains and the SHDN1 or SHDN2 current, typically less than 1A. If unused, connect the SHDN1 and SHDN2 to their corresponding IN pins. Each channel will be in its low power shutdown state if its corresponding SHDN pin is not connected. ADJ1/ADJ2: (Pin 16/Pin 9) Adjust Pin. These are the error amplifier inputs. These pins are internally clamped to 9V. A typical input bias current of 30nA flows into the pins (see curve of ADJ1/ADJ2 Pin Bias Current vs Temperature in the Typical Performance Characteristics section). The ADJ1 and ADJ2 pin voltage is 1.215V referenced to ground and the output voltage range is 1.215V to 19.5V.
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LT3029 APPLICATIONS INFORMATION
The LT3029 is a dual 500mA/500mA low dropout regulator with independent inputs, micropower quiescent current and shutdown. The device supplies up to 500mA from each channel's output at a typical dropout voltage of 300mV. The two regulators share a common GND pin and are thermally coupled. However, the two inputs and outputs of the LT3029 operate independently. Each channel can be shut down independently, but a thermal shutdown fault on either channel shuts off the output on both channels. The addition of a 10nF reference bypass capacitor lowers output voltage noise to 20VRMS over a 10Hz to 100kHz bandwidth. Additionally, the reference bypass capacitor improves transient response of the regulator, lowering the settling time for transient load conditions. The low operating quiescent current (55A per channel) drops to less than 1A in shutdown. In addition to the low quiescent current, the LT3029 regulator incorporates several protection features that make it ideal for use in batterypowered systems. Most importantly, the device protects itself against reverse input voltages. Current limiting with foldback necessitates a minimum load current of 20A for input/output voltage differentials of more than 10V to keep the output regulated. Adjustable Operation Each of the LT3029's channels has an output voltage range of 1.215V to 19.5V. Figure 1 illustrates that output voltage is set by the ratio of two external resistors. The device regulates the output to maintain the corresponding ADJ pin voltage at 1.215V referenced to ground. R1's current equals 1.215V/R1. R2's current equals R1's current plus the ADJ pin bias current. The ADJ pin bias current, 30nA at 25C, flows through R2 into the ADJ pin. Use the formula in Figure 1 to calculate output voltage. Linear Technology recommends that the value of R1 be less than 243k to minimize errors in the output voltage due to the ADJ pin bias current. In shutdown, the output turns off and the divider current is zero. Curves of ADJ Pin Voltage vs Temperature
LT3029 OUT1/OUT2 VIN IN1/IN2 R2 ADJ1/ADJ2 GND R1
3029 F01
VOUT C
R2 VOUT = 1.215V 1+ + IADJ R2 R1 VADJ = 1.215V IADJ = 30nA AT 25C
( )( )
OUTPUT RANGE = 1.215V TO 19.5V O
Figure 1. Adjustable Operation
and ADJ Pin Bias Current vs Temperature appear in the Typical Performance Characteristics section. Linear Technology tests and specifies each LT3029 channel with its ADJ pin tied to the corresponding OUT pin for a 1.215V output voltage. Specifications for output voltages greater than 1.215V are proportional to the ratio of desired output voltage to 1.215V: VOUT 1 . 215V For example, load regulation on either output for an output current change of 1mA to 500mA is typically -2.5mV at VOUT = 1.215V. At VOUT = 2.5V, load regulation is: 2 . 5V * (- 2 . 5mV) = - 5 . 14mV 1 . 215V Table 1 shows 1% resistor divider values for some common output voltages with a resistor divider current of approximately 5A.
Table 1. Output Voltage Resistor Divider Values
VOUT (V) 1.5 1.8 2.5 3 3.3 5 R1 (k) 237 237 243 232 210 200 R2 (k) 54.9 113 255 340 357 619
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12
LT3029 APPLICATIONS INFORMATION
Bypass Capacitance and Low Noise Performance Using a bypass capacitor connected between a channel's BYP pin and its corresponding OUT pin significantly lowers LT3029 output voltage noise, but is not required in all applications. Linear Technology recommends a good quality low leakage capacitor. This capacitor bypasses the regulator's reference, providing a low frequency noise pole. A 10nF bypass capacitor introduces a noise pole that decreases output voltage noise to as low as 20VRMS. Using a bypass capacitor provides the added benefit of improving transient response. With no bypass capacitor, and a 10F output capacitor, a 100mA to 500mA load step settles to within 1% of its final value in approximately 100s. With the addition of a 10nF bypass capacitor and evaluating the same load step, output voltage excursion stays within 1% (see Transient Response in the Typical Performance Characteristics section). Using a bypass capacitor makes regulator start-up time proportional to the value of the bypass capacitor. For example, a 10nF bypass capacitor and 10F output capacitor slow start-up time to 15ms. Output Capacitance and Transient Response The LT3029 design is stable with a wide range of output capacitors. The ESR of the output capacitor affects stability, most notably with small capacitors. Linear Technology recommends a minimum output capacitor of 3.3F with an ESR of 3, or less, to prevent oscillations. The LT3029 is a micropower device, and output transient response is a function of output capacitance. Larger values of output capacitance decrease the peak deviations and provide improved transient response for larger load current changes. Ceramic capacitors require extra consideration. Manufacturers make ceramic capacitors with a variety of dielectrics, each with different behavior across temperature and applied voltage. The most common dielectrics specify the EIA temperature characteristic codes of Z5U, Y5V, X5R and X7R. Z5U and Y5V dielectrics provide high C-V products in a small package at low cost, but exhibit strong voltage and temperature coefficients, as shown in Figures 2 and 3. When used with a 5V regulator, a 16V 10F Y5V capacitor can exhibit an effective value as low as 1F to
20 0 CHANGE IN VALUE (%)
40 BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10F CHANGE IN VALUE (%) X5R 20 0 -20 -40 -60 -80 Y5V X5R
-20 -40 -60 Y5V -80
-100
0
2
4
8 6 10 12 DC BIAS VOLTAGE (V)
14
16
3029 F02
BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10F -100 50 25 75 -50 -25 0 TEMPERATURE (C)
100
125
3029 F03
Figure 2. Ceramic Capacitor DC Bias Characteristics
Figure 3. Ceramic Capacitor Temperature Characteristics
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13
LT3029 APPLICATIONS INFORMATION
2F for the applied DC bias voltage and over the operating temperature range. X5R and X7R dielectrics result in more stable characteristics and are more suitable for use as the output capacitor. The X7R type has better stability across temperature, while the X5R is less expensive and is available in higher values. Exercise care even when using X5R and X7R capacitors; the X5R and X7R codes only specify operating temperature range and maximum capacitance change over temperature. Capacitance change due to DC bias (voltage coefficient) with X5R and X7R capacitors is better than with Y5V and Z5U capacitors, but can still be significant enough to drop capacitor values below appropriate levels. Capacitor DC bias characteristics tend to improve as case size increases. Linear Technology recommends verifying expected versus actual capacitance values at operating voltage in situ for an application.
COUT = 10F CBYP = 0.01F ILOAD = 500mA
Voltage and temperature coefficients are not the only sources of problems. Some ceramic capacitors have a piezoelectric response. A piezoelectric device generates voltage across its terminals due to mechanical stress, similar to the way a piezoelectric accelerometer or microphone works. For a ceramic capacitor, the stress can be induced by vibrations in the system or thermal transients. The resulting voltages produced can cause appreciable amounts of noise, especially when a ceramic capacitor is used for noise bypassing. A ceramic capacitor produced Figure 4's trace in response to light tapping from a pencil. Similar vibration induced behavior can masquerade as increased output voltage noise.
VOUT 500V/DIV
100ms/DIV
3029 F04
Figure 4. Noise Resulting from Tapping on a Ceramic Capacitor
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14
LT3029 APPLICATIONS INFORMATION
Thermal Considerations The LT3029's power handling capability limits the maximum rated junction temperature (125C, LT3029E/LT3029I/ LT3029MP or 150C, LT3029H). Two components comprise the power dissipated by each channel: 1. Output current multiplied by the input/output voltage differential: (IOUT)(VIN - VOUT), and 2. GND pin current multiplied by the input voltage: (IGND)(VIN). Ground pin current is found by examining the GND Pin Current curves in the Typical Performance Characteristics section. Power dissipation for each channel equals the sum of the two components listed above. Total power dissipation for the LT3029 equals the sum of the power dissipated by each channel. The LT3029's internal thermal shutdown circuitry protects both channels of the device if either channel experiences an overload or fault condition. Activation of the thermal shutdown circuitry turns both channels off. If the overload or fault condition is removed, both outputs are allowed to turn back on. For continuous normal conditions, do not exceed the maximum junction temperature rating of 125C (LT3029E/LT3029I/LT3029MP) or 150C (LT3029H). Carefully consider all sources of thermal resistance from junction-to-ambient, including additional heat sources mounted in proximity to the LT3029. For surface mount devices, use the heat spreading capabilities of the PC board and its copper traces to accomplish heat sinking. Copper board stiffeners and plated through-holes can also spread the heat generated by power devices. The following tables list thermal resistance as a function of copper area in a fixed board size. All measurements were taken in still air on a four-layer FR-4 board with 1oz solid internal planes, and 2oz external trace planes with a total board thickness of 1.6mm. For further information on thermal resistance and using thermal information, refer to JEDEC standard JESD51, notably JESD51-12.
Table 2. DE Package, 16-Lead DFN
COPPER AREA TOPSIDE* 2500mm2 1000mm2 225mm2 100mm2 BACKSIDE 2500mm2 2500mm2 2500mm2 2500mm2 THERMAL RESISTANCE BOARD AREA (JUNCTION-TO-AMBIENT) 2500mm2 2500mm2 2500mm2 2500mm2 36C/W 37C/W 38C/W 40C/W
*Device is mounted on topside.
Table 3. MSE Package, 16-Lead MSOP
COPPER AREA TOPSIDE* 2500mm2 1000mm2 225mm2 100mm2 BACKSIDE 2500mm2 2500mm2 2500mm2 2500mm2 THERMAL RESISTANCE BOARD AREA (JUNCTION-TO-AMBIENT) 2500mm2 2500mm2 2500mm2 2500mm2 35C/W 36C/W 37C/W 39C/W
*Device is mounted on topside.
The junction-to-case thermal resistance (JC), measured at the Exposed Pad on the back of the die, is 4.3C/W for the DFN package, and 5C/W to 10C/W for the MSOP package.
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15
LT3029 APPLICATIONS INFORMATION
Calculating Junction Temperature Example: Channel 1's output voltage is set to 1.8V. Channel 2's output voltage is set to 1.5V. Each channel's input voltage is 2.5V. Each channel's output current range is 0mA to 500mA. The application has a maximum ambient temperature of 50C. What is the LT3029's maximum junction temperature? The power dissipated by each channel equals: IOUT(MAX)(VIN - VOUT) + IGND(VIN) where for each output: IOUT(MAX) = 500mA VIN = 2.5V IGND at (IOUT = 500mA, VIN = 2.5V) = 8.5mA So, for output 1: P = 500mA (2.5V - 1.8V) + 8.5mA (2.5V) = 0.37W For output 2: P = 500mA (2.5V - 1.5V) + 8.5mA (2.5V) = 0.52W The thermal resistance is in the range of 35C/W to 40C/W, depending on the copper area. So, the junction temperature rise above ambient temperature approximately equals: (0.37W + 0.52W) 39C/W = 34.7C The maximum junction temperature then equals the maximum ambient temperature plus the maximum junction temperature rise above ambient temperature, or: TJMAX = 50C + 34.7C = 84.7C Protection Features The LT3029 regulator incorporates several protection features that make it ideal for use in battery-powered circuits. In addition to the normal protection features associated with monolithic regulators, such as current limiting and thermal limiting, the device protects itself against reverse input voltages and reverse voltages from output to input. The two regulators have independent inputs, a common GND pin and are thermally coupled. However, the two channels of the LT3029 operate independently. Each channel's output can be shut down independently, and a fault condition on one output does not affect the other output electrically, unless the thermal shutdown circuitry is activated. Current limit protection and thermal overload protection protect the device against current overload conditions at each output of the LT3029. For normal operation, do not allow the junction temperature to exceed 125C (LT3029E/ LT3029I/LT3029MP) or 150C (LT3029H). The typical thermal shutdown temperature threshold is 165C and the circuitry incorporates approximately 5C of hysteresis. Each channel's input withstands reverse voltages of 22V. Current flow into the device is limited to less than 1mA (typically less than 100A) and no negative voltage appears at the respective channel's output. The device protects both itself and the load against batteries that are plugged in backwards. The LT3029 incurs no damage if either channel's output is pulled below ground. If the input is left open-circuit, or grounded, the output can be pulled below ground by
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16
LT3029 APPLICATIONS INFORMATION
22V. The output acts like an open circuit, and no current flows from the output. However, current flows in (but is limited by) the external resistor divider that sets the output voltage. The LT3029 incurs no damage if either ADJ pin is pulled above or below ground by 9V. If the input is left open circuit or grounded, the ADJ pins perform like an open circuit down to -1.5V, and then like a 1.2k resistor down to -9V when pulled below ground. When pulled above ground, the ADJ pins perform like an open circuit up to 0.5V, then like a 5.7k resistor up to 3V, then like a 1.8k resistor up to 9V. In situations where an ADJ pin connects to a resistor divider that would pull the pin above its 9V clamp voltage if the output is pulled high, the ADJ pin input current must be limited to less than 5mA. For example, assume a resistor divider sets the regulated output voltage to 1.5V, and the output is forced to 20V. The top resistor of the resistor divider must be chosen to limit the current
5.0 TJ = 25C 4.5 VIN = 0V = VOUT V 4.0 ADJ 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 1 2 3 IOUT 4 5 6 7 8 9 OUTPUT VOLTAGE (V) IADJ FLOWS INTO ADJ PIN TO GND PIN IOUT FLOWS INTO OUT PIN TO IN PIN
3029 F05
into the ADJ pin to less than 5mA when the ADJ pin is at 9V. The 11V difference between the OUT and ADJ pins divided by the 5mA maximum current into the ADJ pin yields a minimum top resistor value of 2.2k. In circuits where a backup battery is required, several different input/output conditions can occur. The output voltage may be held up while the input is either pulled to ground, pulled to some intermediate voltage or is left open-circuit. Current flow back into the output follows the curve shown in Figure 5. If either of the LT3029's IN pins is forced below its corresponding OUT pin, or the OUT pin is pulled above its corresponding IN pin, input current for that channel typically drops to less than 2A. This occurs if the IN pin is connected to a discharged (low voltage) battery, and either a backup battery or a second regulator circuit holds up the output. The state of that channel's SHDN pin has no effect on the reverse output current if the output is pulled above the input.
REVERSE CURRENT (mA)
IADJ
Figure 5. Reverse Output Current
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17
LT3029 PACKAGE DESCRIPTION
DE Package 16-Lead Plastic DFN (4mm x 3mm)
(Reference LTC DWG # 05-08-1732 Rev O)
0.70 0.05 3.60 0.05 2.20 0.05 3.30 0.05 1.70 0.05 PACKAGE OUTLINE 0.25 0.05 0.45 BSC 3.15 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 0.10 (2 SIDES) R = 0.05 TYP 3.00 0.10 (2 SIDES) PIN 1 TOP MARK (SEE NOTE 6)
R = 0.115 TYP 9
0.40 0.10 16
3.30 0.10 1.70 0.10 PIN 1 NOTCH R = 0.20 OR 0.35 x 45 CHAMFER
(DE16) DFN 0806 REV O
8 0.200 REF 0.75 0.05 3.15 REF 0.00 - 0.05
1 0.23 0.05 0.45 BSC
BOTTOM VIEW--EXPOSED PAD
NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
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18
LT3029 PACKAGE DESCRIPTION
MSE Package 16-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1667 Rev A)
BOTTOM VIEW OF EXPOSED PAD OPTION 2.845 (.112 0.102 .004)
0.889 (.035
0.127 .005)
2.845 (.112 1
0.102 .004) 8 0.35 REF
5.23 (.206) MIN
1.651 (.065
0.102 3.20 - 3.45 .004) (.126 - .136)
1.651 (.065
0.102 .004)
0.12 REF
0.305 0.038 (.0120 .0015) TYP
0.50 (.0197) BSC
16 4.039 0.102 (.159 .004) (NOTE 3)
DETAIL "B" CORNER TAIL IS PART OF DETAIL "B" THE LEADFRAME FEATURE. FOR REFERENCE ONLY 9 NO MEASUREMENT PURPOSE
RECOMMENDED SOLDER PAD LAYOUT
16151413121110 9
0.280 0.076 (.011 .003) REF
0.254 (.010) GAUGE PLANE
DETAIL "A" 0 - 6 TYP 4.90 0.152 (.193 .006) 3.00 0.102 (.118 .004) (NOTE 4)
0.53 0.152 (.021 .006) DETAIL "A" 0.18 (.007) 12345678 1.10 (.043) MAX 0.86 (.034) REF
SEATING PLANE
NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.17 -0.27 (.007 - .011) TYP
0.50 (.0197) BSC
0.1016 (.004
0.0508 .002)
MSOP (MSE16) 0608 REV A
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LT3029 TYPICAL APPLICATION
Coincident Tracking Supply Application
3.3V 0.1F OFF ON VCC ON GATE CGATE 0.1F 3.3V 3.3F BYP1 ADJ1 LT3029 SHDN1 2.5V TRACK1 90.9k 1% 54.9k 1% 63.4k 1% TRACK2 FB2 GND SDO 3.3F IN2 OUT2 10nF BYP2 SHDN2 ADJ2 GND 54.9k 1% 237k 1%
3029 TA02
IN1
OUT1 10nF 113k 1% 237k 1%
VOUT1 1.8V 3.3F 500mA VOUT1 VOUT2 500mV/DIV
RAMP LTC2923 1M
RAMPBUF FB1 113k 1%
VOUT2 3.3F 1.5V 500mA 10ms/DIV
3029 TA02b
RELATED PARTS
PART NUMBER LT1761 LT1763 LT1963/ LT1963A LT1964 LT1965 DESCRIPTION 100mA, Low Noise Micropower LDO 500mA, Low Noise Micropower LDO 1.5A, Low Noise, Fast Transient Response LDOs 200mA, Low Noise Micropower, Negative LDO 1.1A, Low Noise LDO COMMENTS VIN : 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.3V, IQ = 20A, ISD < 1A, Low Noise < 20VRMS, Stable with 1F Ceramic Capacitors, ThinSOTTM Package VIN : 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.3V, IQ = 30A, ISD < 1A, Low Noise < 20VRMS, S8 and DFN Packages VIN : 2.1V to 20V, VOUT(MIN) = 1.21V, VDO = 0.34V, IQ = 1mA, ISD < 1A, Low Noise: < 40VRMS, "A" Version Stable with Ceramic Capacitors; DD, TO220-5, SOT223, S8 and TSSOP Packages VIN : -1.9V to -20V, VOUT(MIN) = -1.22V, VDO = 0.34V, IQ = 30A, ISD = 3A, Low Noise: <30VRMS, Stable with Ceramic Capacitors, ThinSOT Package VIN : 1.8V to 20V, VOUT(MIN) = 1.20V, VDO = 0.31V, IQ = 0.5mA, ISD < 1A, Low Noise: <40VRMS, Stable with Ceramic Capacitors; 3mm x 3mm DFN, MS8E, DD-Pak and TO-220 Packages VIN : 0.9V to 10V, VOUT(MIN) = 0.20V, VDO = 0.15V, IQ = 120A, ISD < 3A; 3mm x 3mm DFN and MS8 Packages VIN : 0.9V to 10V, VOUT(MIN) = 0.20V, VDO = 0.16V, IQ = 120A, ISD < 3A; 5mm x 5mm DFN and SO8 Packages VIN : 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.30V, IQ = 40A, ISD < 1A; DFN and MS10E Packages VIN : 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.30V, IQ = 60A, ISD < 1A; DFN and TSSOP-16E Packages VIN : 0.9V to 5.5V, Low IQ: 54A, Low Noise < 80VRMS, 45mV Dropout Voltage; 2mm x 2mm 6-Lead DFN Package VIN : 1.14V to 5.5V, Low IQ: 950A, Low Noise < 110VRMS, 100mV Dropout Voltage; 10-Lead 3mm x 3mm DFN and MS10E Packages VIN : 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.30V, IQ = 50A, ISD < 1A; DFN and MS10E Packages
LT3020 LT3021 LT3023 LT3024 LTC3025 LTC3026 LT3027 LT3028 LT3080/ LT3080-1
100mA, Low Voltage VLDO 500mA, Low Voltage VLDO Dual 100mA, Low Noise, Micropower LDO Dual 100mA/500mA, Low Noise, Micropower LDO 300mA, Low Voltage Micropower VLDO 1.5A, Low Input Voltage VLDO Dual 100mA, Low Noise, Micropower LDO with Independent Inputs
Dual 100mA/500mA, Low Noise, Micropower VIN : 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.32V, IQ = 60A, ISD < 1A; LDO with Independent Inputs DFN and TSSOP-16E Packages 1.1A, Parallelable, Low Noise LDO VIN : 1.2V to 36V, VOUT: 0V to 35.7V, Low Noise < 40VRMS, 300mV Dropout Voltage (2-Supply Operation), Current-Based Reference with 1-Resistor VOUT Set, Directly Parallelable (No Op Amp Required), Stable with Ceramic Capacitors; TO-220, SOT-223, MS8E and 3mm x 3mm DFN Packages
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ThinSOT is a trademark of Linear Technology Corporation.
20 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
LT 0110 * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2010

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